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d a t a sh eet preliminary speci?cation supersedes data of 1998 feb 18 file under integrated circuits, ic02 1998 sep 07 integrated circuits SAA7212 integrated mpeg avg decoder
1998 sep 07 2 philips semiconductors preliminary speci?cation integrated mpeg avg decoder SAA7212 features general features single external synchronous dram organized as1m 16 interfacing at 81 mhz. due to efficient memory use in mpeg decoding, more than 1 mbit available for graphics fast 16-bit data + 8-bit address interface with external controller on 27 mhz. sustained data rate to external sdram 9 mbytes/s in bursts of 128 bytes dedicated input for audio and video in pes or es in byte wide. data input rate: 9 mbytes/s in byte mode. accompanying strobe signals distinguish between audio and video data dedicated compressed data input compatible with the vlsi ves2020/2030 demultiplexers; video is received in byte format and audio serially audio and/or video can also be input via the cpu interface in pes/es in 8 or 16-bit parallel format up to a peak data rate of 9 mbytes/s single 27 mhz external clock for time base reference and internal processing. internal system time base at 90 khz can be synchronized via cpu port. all required decoding and presentation clocks are generated internally flexible memory allocation under control of the external cpu enables optimized partitioning of memory for different tasks boundary scan testing implemented external sdram self test supply voltage 3.3 v package qfp160. cpu related features 16 bits data, 8 bits address, or 16 bits multiplexed bus. motorola 68xxx and intel x 86 compatible. support fast dma transfer flexible bidirectional interface to external sdram. minimum sustained rate is 9 mbytes/s enhanced block mover allows 3 d data move in the external sdram. picture move/graphic bit maps construction can be done with minimum cpu support. mpeg2 system features parsing of mpeg2 pes and mpeg1 packet streams double system time clock counters stand-alone or supervised audio/video synchronization processing of errors flagged by channel decoding section support for retrieval of pes header. mpeg2 video features decoding of mpeg2 video up to main level, main profile output picture format: ccir-601 4:2:2 interlaced pictures. picture format 720 576 at 50 hz or 720 480 at 60 hz support of constant and variable bit rates up to 15 mbits/s stand-alone or cpu controlled mode for decoding/display processes stand-alone mode can be used by applications requiring still pictures manipulations output interface at 8-bit wide, 27 mhz uyvy multiplexed bus horizontal and vertical pan and scan allows the extraction of a window from the coded picture flexible horizontal scaling from 0.5 up to 4 allows easy aspect ratio conversion including support for 2.21 : 1 aspect ratio movies. in case of shrinking an anti-aliasing pre-filter is applied vertical scaling with fixed factors 0.5, 1 or 2. factor 0.5, realizing picture shrink. factor 2 can be used for up-conversion of pictures with 288 (240) lines or less. vertical down-scaling with 0.75 factor, realizing letter box conversion horizontal and vertical scaling can be combined to scale pictures to 1 4 their original size, thus freeing up screen space for graphic applications like electronic program guides non full screen mpeg pictures will be displayed in a box of which position and background colour are adjustable by the external microcontroller nominal video input buffer size for ml@mp 2.7 mbit video output may be slaved to internally (master) generated or externally (slave) supplied hv synchronization signals. the position of active video is programmable. display phase is not affected by mpeg timebase changes.
1998 sep 07 3 philips semiconductors preliminary speci?cation integrated mpeg avg decoder SAA7212 video output direct connectable to saa718x encoder family various trick modes under control of external microcontroller in stand-alone mode: C freeze field/frame on i or p pictures; restart on i picture C freeze field on b pictures; restart on the next i or p picture. C scanning and decoding of i or i + p pictures in a ibp sequence C single step mode C repeat/skip field for time base correction. mpeg2 audio features decoding of 2 channels, layer i and ii mpeg audio. support for mono, stereo, intensity stereo and dual channel mode. constant and variable bit rates up to 448 kbit/s supported audio sampling frequencies: 48, 44.1, 32, 24, 22.05 and 16 khz crc error detection 3 decoding modes for dual channel streams: decoding of ch1 only, decoding of ch2 only and decoding of both ch1 and ch2 storage of last 54 bytes in ancillary data field dynamic range control (drc) at output independent channel volume control and programmable inter channel crosstalk through a baseband audio processing unit muting possibility via external controller. automatic muting in case of errors or data lack. generation of beeps with programmable tone height, duration and amplitude serial two channel digital audio output with 16, 18, 20 or 22 bits per sample, compatible either to i 2 s or japanese formats. output can be set to high-impedance mode via the external controller. serial spdif audio output. output can be set to high-impedance mode. clock output 256 or 384 f s for external da converter. output can be set to high-impedance mode. audio fifo in external sdram. programmable buffer size, at least 64 kbit is available. synchronization modes: pts controlled, pts free running, software controlled, buffer controlled pts register can be set via external controller programmable processing delay compensation software controlled stop and restart functions. graphics features graphics are presented in boxes independent of video format screen arrangement of boxes is determined by display list mechanism which allows for multiple boxes, background loading, fast switching, scrolling and fading of regions support of 2, 4, 8-bit/pixel in fixed bit maps format or coded in accordance to the dvb variable/run length standard for region based graphics display colours are obtained via colour look up tables. clut output is yuvt at 8-bit for each signal component thus enabling 16 m different colours and 6-bit for t which gives 64 mixing levels with video, (t = transparency). bit-map table mechanism to specify a sub set of entries if the clut is larger than required by the coded bit pattern. supported bit-map tables are 16 to 256, 4 to 256 and 4 to 16. graphics boxes may not overlap vertically. if 256 entry clut has to be down loaded, a vertical separation of 1 line is mandatory. optimized memory utilization in mpeg video decoding allows for a storage capacity of 1.2 mbit for graphics bit maps. flexibility in memory control enables larger capacity in a lot of applications. moreover variable length/run length encoding makes better use of available memory capacity for graphics bit maps thus making full screen graphics at 8-bit/pixel feasible. fast cpu access (9 mbytes/s) enables full 1.2 mbit bit map update within 20 ms internal support for fast block moves in external sdram graphics mechanism can be used for signal generation in the vertical blanking interval. useful for teletext, wide screen signalling, closed caption, etc. support for a single down loadable cursor of 1k pixel with programmable shape. supported shapes are 8 128 pixels, 16 64 pixels, 32 32 pixels, 64 16 pixels and 128 8 pixels. cursor colours obtained via 4 entry clut with yuvt at 6,4,4 respectively 2 bits. mixing of cursor with video + graphics in 4 levels. cursor can be moved freely across the screen without overlapping restrictions.
1998 sep 07 4 philips semiconductors preliminary speci?cation integrated mpeg avg decoder SAA7212 applications tbf. general description the SAA7212 is an mpeg2 source decoder which combines audio decoding and video decoding. additionally to these basic mpeg functions it also provides means for enhanced graphics and/or on-screen display (osd). due to an optimized architecture for audio and video decoding, maximum capacity in external memory and processing power from the external cpu is available for graphics support. quick reference data ordering information symbol parameter min. typ. max. unit v dd functional supply voltage 3.0 3.3 3.6 v i dd(tot) total supply current; v dd = 3.3 v - tbf - ma f clk device clock frequency - 30 ppm 27.0 +30 ppm mhz type number package name description version SAA7212h qfp160 plastic quad ?at package; 160 leads (lead length 1.95 mm); body 28 28 3.4 mm; high stand-off height sot322-1
1998 sep 07 5 philips semiconductors preliminary speci?cation integrated mpeg avg decoder SAA7212 block diagram fig.1 block diagram. memory interface audio/video interface sdram to/from to digital encoder display to audio dac decoder audio system time base unit graphics unit cpu unit external decoder video clock jtag generation buffer and sync video input from demux buffer and sync audio input host interface sdram access unit
1998 sep 07 6 philips semiconductors preliminary speci?cation integrated mpeg avg decoder SAA7212 pinning symbol pin description mux 1 multiplexed/non multiplexed bus cpu_type 2 intel/motorola selection dma_ack 3 dma acknowledge dma_req 4 dma request dma_done 5 dma end dma_rdy 6 dma ready v ss 7 ground for pad ring cs 8 chip select. ds 9 data strobe as 10 address strobe rwn 11 read/write dtack 12 data acknowledge v dd 13 3.3 v supply for pad ring irq 0 14 individually maskable interrupts irq 1 15 individually maskable interrupts v_req 16 compressed video data request a_req 17 compressed audio data request v ss 18 ground for pad ring v ssco 19 ground for core logic v ddco 20 3.3 v supply for core logic data 0 21 cpu data interface data 1 22 cpu data interface data 2 23 cpu data interface data 3 24 cpu data interface v dd 25 3.3 v supply for pad ring data 4 26 cpu data interface data 5 27 cpu data interface data 6 28 cpu data interface data 7 29 cpu data interface v ss 30 ground for pad ring data 8 31 cpu data interface data 9 32 cpu data interface data 10 33 cpu data interface data 11 34 cpu data interface v dd 35 3.3 v supply for pad ring data 12 36 cpu data interface data 13 37 cpu data interface data 14 38 cpu data interface data 15 39 cpu data interface v ss 40 ground for pad ring
1998 sep 07 7 philips semiconductors preliminary speci?cation integrated mpeg avg decoder SAA7212 address 1 41 cpu address interface address 2 42 cpu address interface address 3 43 cpu address interface address 4 44 cpu address interface v dd 45 3.3 v supply for pad ring address 5 46 cpu address interface address 6 47 cpu address interface address 7 48 cpu address interface address 8 49 cpu address interface v ss 50 ground for pad ring v ssco 51 ground for core logic v ddco 52 3.3 v supply for core logic sdram_data 0 53 sdram data sdram_data 15 54 sdram data sdram_data 1 55 sdram data v dd 56 3.3 v supply for pad ring sdram_data 14 57 sdram data sdram_data 2 58 sdram data sdram_data 13 59 sdram data v ss 60 ground for pad ring sdram_data 3 61 sdram data sdram_data 12 62 sdram data sdram_data 4 63 sdram data v dd 64 3.3 v supply for pad ring sdram_data 11 65 sdram data sdram_data 5 66 sdram data sdram_data 10 67 sdram data v ss 68 ground for pad ring sdram_data 6 69 sdram data sdram_data 9 70 sdram data sdram_data 7 71 sdram data v dd 72 3.3 v supply for pad ring sdram_data 8 73 sdram data sdram_we 74 sdram write enable sdram_cas 75 sdram column address strobe v ss 76 ground for pad ring sdram_ras 77 sdram row address strobe sdram_udq 78 sdram write mask v dd 79 3.3 v supply for pad ring read_in 80 read command in read_out 81 read command out symbol pin description
1998 sep 07 8 philips semiconductors preliminary speci?cation integrated mpeg avg decoder SAA7212 v ss 82 ground for pad ring cp81mext 83 81 mhz sdram clock return path cp81m 84 81 mhz sdram memory clock v dd 85 3.3 v supply for pad ring sdram_addr 8 86 sdram address sdram_addr 9 87 sdram address sdram_addr 11 88 sdram address v ss 89 ground for pad ring sdram_addr 7 90 sdram address sdram_addr 10 91 sdram address sdram_addr 6 92 sdram address v dd 93 3.3 v supply for pad ring sdram_addr 0 94 sdram address sdram_addr 5 95 sdram address sdram_addr 1 96 sdram address v ss 97 ground for pad ring sdram_addr 4 98 sdram address sdram_addr 2 99 sdram address sdram_addr 3 100 sdram address v ssco 101 ground for core logic v ddco 102 3.3 v supply for core logic v dd 103 3.3 v supply for pad ring test 5 104 ic test interface (see note 2) test 6 105 ic test interface (see note 2) hs 106 horizontal synchronization vs 107 vertical synchronization v ss 108 ground for pad ring yuv 0 109 yuv video output at 27 mhz yuv 1 110 yuv video output at 27 mhz yuv 2 111 yuv video output at 27 mhz yuv 3 112 yuv video output at 27 mhz v dd 113 3.3 v supply for pad ring yuv 4 114 yuv video output at 27 mhz yuv 5 115 yuv video output at 27 mhz yuv 6 116 yuv video output at 27 mhz yuv 7 117 yuv video output at 27 mhz test 4 118 ic test interface (see note 3) grph 119 indicator for graphics information test 3 120 ic test interface (see note 4) v ddan 121 3.3 v supply for analog blocks v ssan 122 ground for analog blocks symbol pin description
1998 sep 07 9 philips semiconductors preliminary speci?cation integrated mpeg avg decoder SAA7212 v ss 123 ground for pad ring clk 124 27 mhz clock input v ss 125 ground for pad ring tck 126 boundary scan test clock trst 127 boundary scan test reset tms 128 boundary scan test mode select tdo 129 boundary scan test data output tdi 130 boundary scan test data input v dd 131 3.3 v supply for pad ring test 0 132 ic test interface (see note 4) test 1 133 ic test interface (see note 4) test 2 134 ic test interface (see note 4) audden 135 synchronization of the serial audio input (a_data) a_data 136 serial audio input v dd 137 3.3 v supply for pad ring reset 138 hard reset input, active low fsclk 139 256 or 384f s (audio sampling) v ddco 140 3.3 v supply for core logic v ssco 141 ground for core logic sck 142 serial audio clock sd 143 serial audio data output v ss 144 ground for pad ring ws 145 word select spdif 146 digital audio output error 147 ?ag for bitstream error. v_strobe 148 video strobe v dd 149 3.3 v supply for pad ring av_data 0 150 mpeg stream input port av_data 1 151 mpeg stream input port av_data 2 152 mpeg stream input port av_data 3 153 mpeg stream input port v ss 154 ground for pad ring av_data 4 155 mpeg stream input port av_data 5 156 mpeg stream input port av_data 6 157 mpeg stream input port av_data 7 158 mpeg stream input port a_strobe 159 audio strobe v dd 160 3.3 v supply for pad ring symbol pin description
1998 sep 07 10 philips semiconductors preliminary speci?cation integrated mpeg avg decoder SAA7212 notes 1. 5 v tolerant outputs swing between v ss and v dd but 5 v tolerant input can receive signal swinging between v ss and 3.3 v or v ss and 5 v. 2. should be left open in normal mode. 3. should be tied up to v dd in normal mode. 4. should be tied down to ground in normal mode. fig.2 pin configuration. handbook, halfpage SAA7212h 1 160 121 41 80 40 120 81 mgl400
1998 sep 07 11 philips semiconductors preliminary speci?cation integrated mpeg avg decoder SAA7212 limiting values in accordance with the absolute maximum rating system (iec 134). thermal characteristics handling inputs and outputs are protected against electrostatic discharges in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. characteristics symbol parameter conditions min. typ. max. unit v dd supply voltage - 0.5 +5 tbf v v n(max) voltage on all pins 0 5 tbf v p tot total power dissipation t amb =25 c - 1 tbf w t stg ic storage temperature - 55 150 tbf c t amb operating ambient temperature 0 70 tbf c symbol parameter value unit r th(j-a) thermal resistance from junction to ambient in free air 30 k/w symbol parameter min. typ. max. unit supply v dd functional supply voltage 3.0 3.3 3.6 v i dd(tot) total supply current; v dd = 3.3 v - tbf - ma inputs v ih(5v tolerant) input voltage high 2.0 - 6.5 v v ih input voltage high 0.7v dd - v dd +2.0 v v il(5v tolerant) input voltage low - 0.5 - 0.8 v v il input voltage low - 0.5 - 0.3v dd v i l leakage current -- 20 m a c i input capacitance 0 - 10 pf outputs v oh(5v tolerant) output voltage high 2.4 -- v v oh output voltage high v dd - 0.4 -- v v ol(5v tolerant) output voltage low -- 0.4 v v ol output voltage low -- 0.4 v dc timing t cy cycle time - 37.037 - ns d duty factor 40 - 60 %
1998 sep 07 12 philips semiconductors preliminary speci?cation integrated mpeg avg decoder SAA7212 application information fig.3 application diagram cvbs h,v yuv i 2 s audio d/a l r 8 valid strobe SAA7212 27 mhz 4-mbit dram 16-mbit sdram ttx/ttxrq high data 4-mbit eprom speed 27.0 mhz i 2 c-bus 16 16 h,v,fp saa7183 y/c rgb (euro-denc) 8+3 irq 12 ctrl data addr 2 4 cpu + demux
1998 sep 07 13 philips semiconductors preliminary speci?cation integrated mpeg avg decoder SAA7212 fig.4 connection SAA7212 sdram. sdram 16-mbit dq0 dq15 .... a7 a0 .... cas a11 a10 a9 a8 ras cs we udqm ldqm cke clk tssop ii 50 pins 400 mil sdram_data0 sdram_data15 ....... sdram_addr7 sdram_addr0 .... sdram_cas sdram_addr11 sdram_addr10 sdram_addr9 sdram_addra8 sdram_ras sdram_cs sdram_we sdram_udq cp81m read_in read_out cp81mext the board should be designed to insure a similar load on the cp81m and read_out pins as well as a similar fly time between the cp81m and cp81mext pins on one side and the read_out and read_in pins on the other side.
1998 sep 07 14 philips semiconductors preliminary speci?cation integrated mpeg avg decoder SAA7212 package outline unit a 1 a 2 a 3 b p ce (1) (1) (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.40 0.25 3.70 3.15 0.25 0.40 0.25 0.23 0.13 28.1 27.9 0.65 0.3 1.95 32.2 31.6 1.5 1.1 8 0 o o 0.15 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.1 0.7 sot322-1 mo112dd1 95-02-04 97-08-04 d (1) 28.1 27.9 h d 32.2 31.6 e z 1.5 1.1 d pin 1 index b p e q e a 1 a l p detail x l (a ) 3 b 40 c d h b p e h a 2 v m b d z d a z e e v m a x 1 160 121 120 81 80 41 y w m w m 0 5 10 mm scale sot322-1 160 leads (lead length 1.95 mm); body 28 x 28 x 3.4 mm; high stand-off height qfp160: plastic quad flat package; a max. 3.95
1998 sep 07 15 philips semiconductors preliminary speci?cation integrated mpeg avg decoder SAA7212 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, for qfp packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. caution wave soldering is not applicable for all qfp packages with a pitch (e) equal or less than 0.5 mm.
1998 sep 07 16 philips semiconductors preliminary speci?cation integrated mpeg avg decoder SAA7212 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1998 sep 07 17 philips semiconductors preliminary speci?cation integrated mpeg avg decoder SAA7212 notes
1998 sep 07 18 philips semiconductors preliminary speci?cation integrated mpeg avg decoder SAA7212 notes
1998 sep 07 19 philips semiconductors preliminary speci?cation integrated mpeg avg decoder SAA7212 notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1998 sca60 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors 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novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 printed in the netherlands 545104/750/02/pp20 date of release: 1998 sep 07 document order number: 9397 750 04068

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